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Jaesoo Ahn
Jaesoo Ahn
Applied Materials
Verified email at alumni.stanford.edu
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Year
A Distributed Model for Border Traps in MOS Devices
Y Yuan, L Wang, B Yu, B Shin, J Ahn, PC McIntyre, PM Asbeck, ...
IEEE Electron Device Letters 32 (4), 485-487, 2011
2122011
A Distributed Bulk-Oxide Trap Model forInGaAs MOS Devices
Y Yuan, B Yu, J Ahn, PC McIntyre, PM Asbeck, MJW Rodwell, Y Taur
IEEE Transactions on Electron Devices 59 (8), 2100-2106, 2012
1612012
New method for determining flat-band voltage in high mobility semiconductors
R Winter, J Ahn, PC McIntyre, M Eizenberg
Journal of Vacuum Science & Technology B 31 (3), 2013
1202013
Hybrid carbon hardmask for lateral hardmask recess reduction
TJ Kwon, R Cheng, AB Mallick, EX Ping, AHN Jaesoo
US Patent 9,991,118, 2018
912018
Interface-State Modeling of –InGaAs MOS From Depletion to Inversion
HP Chen, Y Yuan, B Yu, J Ahn, PC McIntyre, PM Asbeck, MJW Rodwell, ...
IEEE Transactions on Electron Devices 59 (9), 2383-2389, 2012
912012
A study on practically unlimited endurance of STT-MRAM
JJ Kan, C Park, C Ching, J Ahn, Y Xie, M Pakala, SH Kang
IEEE Transactions on Electron Devices 64 (9), 3639-3646, 2017
892017
Systematic validation of 2x nm diameter perpendicular MTJ arrays and MgO barrier for sub-10 nm embedded STT-MRAM with practically unlimited endurance
JJ Kan, C Park, C Ching, J Ahn, L Xue, R Wang, A Kontos, S Liang, ...
2016 IEEE International Electron Devices Meeting (IEDM), 27.4. 1-27.4. 4, 2016
642016
Method of forming magnetic tunneling junctions
M Pakala, M Balseanu, J Germain, AHN Jaesoo, XUE Lin
US Patent 9,564,582, 2017
582017
Hard mask for patterning magnetic tunnel junctions
XUE Lin, M Pakala, H Chen, AHN Jaesoo
US Patent App. 14/755,964, 2016
562016
Arsenic decapping and pre-atomic layer deposition trimethylaluminum passivation of Al2O3/InGaAs(100) interfaces
J Ahn, T Kent, E Chagarov, K Tang, AC Kummel, PC McIntyre
Applied Physics Letters 103 (7), 071602, 2013
552013
Electron Mobility in Surface- and Buried-Channel FlatbandMOSFETs With ALDGate Dielectric
SJ Bentley, M Holland, X Li, GW Paterson, H Zhou, O Ignatova, ...
IEEE Electron Device Letters 32 (4), 494-496, 2011
492011
Systematic optimization of 1 Gbit perpendicular magnetic tunnel junction arrays for 28 nm embedded STT-MRAM and beyond
C Park, JJ Kan, C Ching, J Ahn, L Xue, R Wang, A Kontos, S Liang, ...
2015 IEEE International Electron Devices Meeting (IEDM), 26.2. 1-26.2. 4, 2015
482015
Titania/alumina bilayer gate insulators for InGaAs metal-oxide-semiconductor devices
J Ahn, I Geppert, M Gunji, M Holland, I Thayne, M Eizenberg, PC McIntyre
Applied Physics Letters 99 (23), 2011
402011
Effects of oxide thickness and temperature on dispersions in InGaAs MOS CV characteristics
HP Chen, J Ahn, PC McIntyre, Y Taur
Journal of Vacuum Science & Technology B 32 (3), 2014
282014
Comparison of bulk-oxide trap models: lumped versus distributed circuit
HP Chen, J Ahn, PC McIntyre, Y Taur
IEEE transactions on electron devices 60 (11), 3920-3924, 2013
262013
Low RA magnetic tunnel junction arrays in conjunction with low switching current and high breakdown voltage for STT-MRAM at 10 nm and beyond
C Park, H Lee, C Ching, J Ahn, R Wang, M Pakala, SH Kang
2018 IEEE Symposium on VLSI Technology, 185-186, 2018
212018
Process optimization of perpendicular magnetic tunnel junction arrays for last-level cache beyond 7 nm node
L Xue, C Ching, A Kontos, J Ahn, X Wang, R Whig, H Tseng, J Howarth, ...
2018 IEEE Symposium on VLSI Technology, 117-118, 2018
202018
Effect and extraction of series resistance in Al2O3‐InGaAs MOS with bulk‐oxide trap
B Yu, Y Yuan, HP Chen, J Ahn, PC McIntyre, Y Taur
Electronics letters 49 (7), 492-493, 2013
172013
Method of forming metal pattern using selective electroplating process
HJ Lee, JW Lee, DH Hong, S Hah, H Son, JS Chung, JS Ahn
US Patent App. 10/875,434, 2005
172005
The effect of post oxide deposition annealing on the effective work function in metal/Al2O3/InGaAs gate stack
R Winter, I Krylov, J Ahn, PC McIntyre, M Eizenberg
Applied Physics Letters 104 (20), 2014
162014
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