| Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers T Park, S Choi, DH Lee, JR Yoo, BC Lee, JY Kim, CG Lee, KK Chi, ... 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No …, 2003 | 235 | 2003 |
| Method for forming a trench isolation structure in an integrated circuit T Park, H Lee, Y Shin US Patent 6,107,143, 2000 | 175 | 2000 |
| Methods for forming isolation trenches including doped silicon oxide T Park US Patent 5,902,127, 1999 | 89 | 1999 |
| Vertical channel field effect transistors having insulating layers thereon T Park, EJ Yoon, UI Chung, SY Choi, J Lee US Patent 7,148,541, 2006 | 87 | 2006 |
| Characteristics of the full CMOS SRAM cell using body-tied TG MOSFETs (bulk FinFETs) TS Park, HJ Cho, JD Choe, SY Han, D Park, K Kim, E Yoon, JH Lee IEEE Transactions on Electron Devices 53 (3), 481-487, 2006 | 69 | 2006 |
| Methods of forming semiconductor device GH Buh, CW Ryoo, Y Shin, T Park, JW Lee US Patent 7,351,622, 2008 | 68 | 2008 |
| Double gate field effect transistor and method of manufacturing the same JM Yoon, D Park, GY Jin, Y Makoto, T Park US Patent 7,015,106, 2006 | 66 | 2006 |
| PMOS body-tied FinFET (Omega MOSFET) characteristics T Park, D Park, JH Chung, EJ Yoon, SM Kim, HJ Cho, JD Choe, JH Choi, ... 61st Device Research Conference. Conference Digest (Cat. No. 03TH8663), 33-34, 2003 | 60 | 2003 |
| Method of forming shallow trench isolation layer in semiconductor device T Park, H Kang, D Ahn, M Park US Patent 6,482,715, 2002 | 56 | 2002 |
| Methods of forming trench isolation regions having recess-inhibiting layers therein that protect against overetching S Kim, KJ Lee, I Hwang, Y Koh, D Ahn, M Park, T Park US Patent 6,461,937, 2002 | 48 | 2002 |
| A 40nm body-tied FinFET (OMEGA MOSFET) using bulk Si wafer T Park, E Yoon, JH Lee Physica E: Low-dimensional Systems and Nanostructures 19 (1-2), 6-12, 2003 | 46 | 2003 |
| Trench isolation regions having recess-inhibiting layers therein that protect against overetching S Kim, KJ Lee, I Hwang, Y Koh, D Ahn, M Park, T Park US Patent 6,717,231, 2004 | 39 | 2004 |
| Body-tied triple-gate NMOSFET fabrication using bulk Si wafer T Park, S Choi, DH Lee, UI Chung, JT Moon, E Yoon, JH Lee Solid-State Electronics 49 (3), 377-383, 2005 | 36 | 2005 |
| Trench isolation regions having trench liners with recessed ends T Park, M Park, KW Park, H Lee US Patent 6,465,866, 2002 | 36 | 2002 |
| Fin field effect transistor and method of forming the same DH Lee, SG Lee, GH Buh, J Yoo, SY Choi, T Park US Patent App. 11/892,320, 2008 | 30 | 2008 |
| Characteristics of body-tied triple-gate pMOSFETs TS Park, HJ Cho, JD Choe, IH Cho, D Park, E Yoon, JH Lee IEEE electron device letters 25 (12), 798-800, 2004 | 29 | 2004 |
| Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs) T Park, HJ Cho, JD Choe, SY Han, SM Jung, JH Jeong, BY Nam, OI Kwon, ... IEEE International Electron Devices Meeting 2003, 2.2. 1-2.2. 4, 2003 | 29 | 2003 |
| Trench isolation structure, semiconductor device having the same, and trench isolation method T Park, M Park, KW Park, H Lee US Patent 6,331,469, 2001 | 28 | 2001 |
| Silicon nitride-free isolation methods for integrated circuits T Park, H Kang US Patent 5,966,614, 1999 | 28 | 1999 |
| Semiconductor device having a trench isolation structure T Park US Patent 6,617,662, 2003 | 27 | 2003 |
Jong-Ho LeeDepartment of Electrical and Computer Engineering, Seoul National UniversityVerified email at snu.ac.kr
