Pramod Meher

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Basant Kumar MohantyProfessor, Electronics and Telecommunication Engineering, Sambalpur University Institute ofVerified email at suiit.ac.in
Jagdish PatraSwinburne University of Technology, Melbourne, AustraliaVerified email at swin.edu.au
Sang Yoon Parkinstitute for infocomm researchVerified email at i2r.a-star.edu.sg
Chiou-Yng LeeLunghwa University of Science and TechnologyVerified email at gm.lhu.edu.tw
Vinod A PrasadProfessor, Information Communication Technology, Singapore Institute of TechnologyVerified email at singaporetech.edu.sg
Swamy, M.N.S.Propfessor of Electrical and Computer Eng., Concordia UniversityVerified email at ece.concordia.ca
Javier VallsProfesor del Departamento de Ingeniería Electrónica de la Universidad Politécnica de ValenciaVerified email at eln.upv.es
Xin LouShanghaiTech UniversityVerified email at shanghaitech.edu.cn
Jridi MaherEnseignant chercheur, ISEN Yncrea OuestVerified email at isen-ouest.yncrea.fr
Prof. Gananath DashSambalpur UniversityVerified email at ieee.org
Prof. Ganapati Panda (G. Panda)C V Raman Global University-OdishaVerified email at iitbbs.ac.in
Sudha NatarajanProfessor, School of Computing, SASTRA Deemed UniversityVerified email at cse.sastra.edu
Jeng-Shyang Pan (潘正祥)Shandong University of Science and TechnologyVerified email at ieee.org
Mukesh Kumar RavalFormer Professor of Chemistry, Gangadhar Meher College, Sambalpur-768004, Orissa, IndiaVerified email at bsnl.in
Yu PanSingapore perception team lead at nuTonomyVerified email at nutonomy.com
Jitendriya K SatapathyProfessor in Electrical Engineering, National Institute of Technology, Rourkela-769008, IndiaVerified email at nitrkl.ac.in
Dwaipayan RaySenior Lead Engineer at QualcommVerified email at iitgn.ac.in
Nithin GeorgeIndian Institute of Technology GandhinagarVerified email at iitgn.ac.in
subhendu kumar SahooBITS Pilani HyderabadVerified email at hyderabad.bits-pilani.ac.in
Sujit Kumar PatelThapar Institute of Engineering and Technology, Patiala, PunjabVerified email at thapar.edu

Pramod Meher

C V Raman Global University, Bhubaneswar, India

Verified email at sandhaanlabs.in

Low-Power High-Performance and Reconfigurable Systems Table-based Computing and CORDIC Designs for DSP Applications Finite Fie


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50 years of CORDIC: Algorithms, architectures, and applications PK Meher, J Valls, TB Juang, K Sridharan, K Maharatna IEEE Transactions on Circuits and Systems I: Regular Papers 56 (9), 1893-1907, 2009	640	2009
FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic PK Meher, S Chandrasekaran, A Amira IEEE transactions on signal processing 56 (7), 3009-3017, 2008	317	2008
Efficient integer DCT architectures for HEVC PK Meher, SY Park, BK Mohanty, KS Lim, C Yeo IEEE Transactions on Circuits and systems for Video Technology 24 (1), 168-178, 2013	225	2013
New approach to look-up-table design and memory-based realization of FIR digital filter PK Meher IEEE Transactions on Circuits and Systems I: Regular Papers 57 (3), 592-603, 2009	190	2009
Efficient FPGA and ASIC realizations of a DA-based reconfigurable FIR digital filter SY Park, PK Meher IEEE Transactions on Circuits and Systems II: Express Briefs 61 (7), 511-515, 2014	188	2014
A high-performance energy-efficient architecture for FIR adaptive filter based on new distributed arithmetic formulation of block LMS algorithm BK Mohanty, PK Meher IEEE transactions on signal processing 61 (4), 921-932, 2012	133	2012
Low-power, high-throughput, and low-area adaptive FIR filter based on distributed arithmetic SY Park, PK Meher IEEE Transactions on Circuits and Systems II: Express Briefs 60 (6), 346-350, 2013	132	2013
A high-performance FIR filter architecture for fixed and reconfigurable applications BK Mohanty, PK Meher IEEE transactions on very large scale integration (VLSI) systems 24 (2), 444-452, 2015	116	2015
Hardware-efficient systolization of DA-based calculation of finite digital convolution PK Meher IEEE Transactions on Circuits and Systems II: Express Briefs 53 (8), 707-711, 2006	113	2006
Nonlinear channel equalization for wireless communication systems using Legendre neural networks JC Patra, PK Meher, G Chakraborty Signal Processing 89 (11), 2251-2262, 2009	111	2009
FPGA implementation of orthogonal matching pursuit for compressive sensing reconstruction H Rabah, A Amira, BK Mohanty, S Almaadeed, PK Meher IEEE Transactions on very large scale integration (VLSI) Systems 23 (10 …, 2014	110	2014
Efficient CORDIC algorithms and architectures for low area and high throughput implementation L Vachhani, K Sridharan, PK Meher IEEE Transactions on Circuits and Systems II: Express Briefs 56 (1), 61-65, 2009	101	2009
Critical-path analysis and low-complexity implementation of the LMS adaptive algorithm PK Meher, SY Park IEEE Transactions on Circuits and Systems I: Regular Papers 61 (3), 778-788, 2013	96	2013
Memory efficient modular VLSI architecture for highthroughput and low-latency implementation of multilevel lifting 2-D DWT BK Mohanty, PK Meher IEEE Transactions on signal processing 59 (5), 2072-2084, 2011	95	2011
Systolic and Super-Systolic Multipliers for Finite Field Based on Irreducible Trinomials PK Meher IEEE Transactions on Circuits and Systems I: Regular Papers 55 (4), 1031-1040, 2008	90	2008
Memory-Efficient High-Speed Convolution-based Generic Structure for Multilevel 2-D DWT BK Mohanty, PK Meher IEEE Transactions on Circuits and Systems for Video Technology 23 (2), 353-363, 2013	88	2013
On Efficient Implementation of Accumulation in Finite Field Over < formula formulatype= PK Meher Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 17 (4 …, 2009	81*	2009
Legendre-FLANN-based nonlinear channel equalization in wireless communication system JC Patra, WC Chin, PK Meher, G Chakraborty 2008 IEEE international conference on systems, man and cybernetics, 1826-1831, 2008	80	2008
CORDIC Designs for Fixed Angle of Rotation PK Meher, SY Park IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (2), 217-228, 2013	79	2013
High-throughput pipelined realization of adaptive FIR filter based on distributed arithmetic PK Meher, SY Park 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 428-433, 2011	79	2011

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