| 3D-MAPS: 3D massively parallel processor with stacked memory DH Kim, K Athikulwongse, M Healy, M Hossain, M Jung, I Khorosh, ... IEEE International Solid-State Circuits Conference, 2012 | 221 | 2012 |
| 3D floorplanning using 2D and 3D blocks K Samadi, SA Panth, Y Du US Patent 9,064,077, 2015 | 217 | 2015 |
| Clock distribution network for 3D integrated circuit K Samadi, SA Panth, J Xie, Y Du US Patent 9,098,666, 2015 | 174 | 2015 |
| Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro K Samadi, SA Panth, Y Du, RP Gilmore US Patent 10,192,813, 2019 | 165 | 2019 |
| Design and CAD methodologies for low power gate-level monolithic 3D ICs SA Panth, K Samadi, Y Du, SK Lim Proceedings of the 2014 international symposium on Low power electronics and …, 2014 | 138 | 2014 |
| High-density integration of functional modules using monolithic 3D-IC technology S Panth, K Samadi, Y Du, SK Lim 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 681-686, 2013 | 93 | 2013 |
| Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs S Panth, K Samadi, Y Du, SK Lim Proceedings of the 2014 on International symposium on physical design, 47-54, 2014 | 89 | 2014 |
| Power-performance study of block-level monolithic 3D-ICs considering inter-tier performance variations S Panth, K Samadi, Y Du, SK Lim Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 82 | 2014 |
| Design and analysis of 3D-MAPS (3D massively parallel processor with stacked memory) DH Kim, K Athikulwongse, MB Healy, MM Hossain, M Jung, I Khorosh, ... IEEE Transactions on Computers 64 (1), 112-125, 2013 | 80 | 2013 |
| Shrunk-2-D: A physical design methodology to build commercial-quality monolithic 3-D ICs S Panth, K Samadi, Y Du, SK Lim IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 74 | 2017 |
| Fast and accurate thermal modeling and optimization for monolithic 3D ICs SK Samal, S Panth, K Samadi, M Saedi, Y Du, SK Lim Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 74 | 2014 |
| Design challenges and solutions for ultra-high-density monolithic 3D ICs S Panth, S Samal, YS Yu, SK Lim 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S …, 2014 | 52 | 2014 |
| Scan test of die logic in 3-D ICs using TSV probing B Noia, S Panth, K Chakrabarty, SK Lim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (2), 317-330, 2014 | 39 | 2014 |
| Adaptive regression-based thermal modeling and optimization for monolithic 3-D ICs SK Samal, S Panth, K Samadi, M Saeidi, Y Du, SK Lim IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 32 | 2016 |
| Impact of size effects in local interconnects for future technology nodes: A study based on full-chip layouts A Ceyhan, M Jung, S Panth, SK Lim, A Naeemi IEEE International Interconnect Technology Conference, 345-348, 2014 | 30 | 2014 |
| Electrical coupling of monolithic 3-D inverters YS Yu, S Panth, SK Lim IEEE Transactions on Electron Devices 63 (8), 3346-3349, 2016 | 29 | 2016 |
| Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores DL Lewis, S Panth, X Zhao, SK Lim, HHS Lee 2011 IEEE 29th International Conference on Computer Design (ICCD), 90-95, 2011 | 22 | 2011 |
| Isonet: Hardware-based job queue management for many-core architectures J Lee, C Nicopoulos, HG Lee, S Panth, SK Lim, J Kim IEEE transactions on very large scale integration (VLSI) systems 21 (6 …, 2012 | 19 | 2012 |
| Monolithic 3D IC design: Power, performance, and area impact at 7nm K Acharya, K Chang, BW Ku, S Panth, S Sinha, B Cline, G Yeric, SK Lim 2016 17th international symposium on quality electronic design (ISQED), 41-48, 2016 | 18 | 2016 |
| Evaluating Chip-Level Impact of Cu/Low-Performance Degradation on Circuit Performance at Future Technology Nodes A Ceyhan, M Jung, S Panth, SK Lim, A Naeemi IEEE Transactions on Electron Devices 62 (3), 940-946, 2015 | 16 | 2015 |
