| Power integrity for I/O interfaces: with signal integrity/power integrity co-design VS Pandit, WH Ryu, MJ Choi Pearson Education, 2010 | 33 | 2010 |
| Electrical energy absorption in the human head from a cellular telephone V Pandit, R McDermott, G Lazzi, C Furse, O Gandhi Proceedings of Seventh Annual IEEE Visualization'96, 371-374, 1996 | 14 | 1996 |
| Controllable parameters identification for high speed channel through signal-power integrity combined analysis MJ Choi, VS Pandit, WH Ryu 2008 58th Electronic Components and Technology Conference, 658-663, 2008 | 10 | 2008 |
| Simulation and Characterization of GHz on-chip Power Delivery Network VS Pandit, WH Ryu, S Ramanujam, K Pushparaj, F Fattouh DesignCon, 2008 | 8* | 2008 |
| Reduced circuit modeling of mother board and package for a system power delivery analysis J Koo, V Pandit 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging …, 2011 | 5 | 2011 |
| Multi-ghz modeling and characterization of on-chip power delivery network VS Pandit, WH Ryu 2008 IEEE-EPEP Electrical Performance of Electronic Packaging, 115-118, 2008 | 5 | 2008 |
| SI-PD Co-simulation and Co-design Methodology for High Speed Channel MJ Choi, VS Pandit, WH Ryu 2007 IEEE Electrical Performance of Electronic Packaging, 123-126, 2007 | 5 | 2007 |
| SSO Noise, Eye Margin, and Jitter Characterization for I/O Power Integrity V Pandit, AN Pardiwala, H Chuang, MJ Choi, MR Quddus IEC DesignCon 2009, 2009 | 4 | 2009 |
| Electrical Integrity for LPDDR5 Memory Technology V Pandit, A Pious, P Ranjan, A Rajasekaran, K Kamisetty, J Liao, ... DesignCon 2019, 2019 | 2 | 2019 |
| An efficient Power Integrity design methodology to prevent Platform failures for high density designs V Ragavassamy, J He, A Kandasamy, YL Li, V Pandit DesignCon 2013, 2013 | 2 | 2013 |
| Power Integrity for Single Ended System V Pandit, MJ Choi IBIS summit, June 2008, 2008 | 2 | 2008 |
| Simulation and visualization for bioelectromagnetic problems VS Pandit Department of Electrical Engineering, University of Utah, 1996 | 2 | 1996 |
| Supply Noise and Jitter for Multi-GT/s Single-ended Interface V Pandit, T Wang, Xiaoqing, Pham, A Martin DesignCon 2011, 2011 | 1 | 2011 |
| System Design Challenges with 5G and mmWave Integration KC Maruti Tamrakar, K Tarakesava, Jay Vishnu Gupta, Aiswarya Pious, Vishram ... DesignCon 2023, 2023 | | 2023 |
| A Comparison of Motherboard Voltage Regulator and Fully Integrated Voltage Regulator for Power and Performance Optimized Solution,” G Jayanth Kalyan, Vishram Pandit, Ashwini, Andrea DesignCon 2022, 2022 | | 2022 |
| System Co-design for Sleek Detachable/ Tablet Reference Design,” KC Tarakesava K, Aiswarya Pious, Jayanth Kalyan, Vishram Pandit, Yagnesh ... DesignCon 2022, 2022 | | 2022 |
| Electrical Optimizations for Small Form Factor Systems YW Vishram Pandit, Aiswarya Pious, Arunthathi Chandrabose, Jayanth Kalyan ... DesignCon 2021, 2021 | | 2021 |
| Achieving Power Integrity Solutions while Integrating Various I/Ps Praveen Pai, Vishram Pandit, Lokender S., Geeta V. DesignCon 2020, 2020 | | 2020 |
| DDR Memory Technologies: A System Designer Perspective R Parthasarathy, V Pandit EDAPS (Electrical Design of Advanced Packaging and Systems) 2018, 2018 | | 2018 |
| Novel Isolation Scheme for Mitigating PDN coupling A Waizman, V Pandit, V Kasturi, M Peterburg Alzaradel DesignCon 2018, 2018 | | 2018 |
