| Fast and effective placement and routing directed high-level synthesis for FPGAs H Zheng, ST Gurumani, K Rupnow, D Chen Proceedings of the 2014 ACM/SIGDA international symposium on Field …, 2014 | 54 | 2014 |
| High-level synthesis with behavioral-level multicycle path analysis H Zheng, ST Gurumani, L Yang, D Chen, K Rupnow IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 39 | 2014 |
| 1024-point pipeline FFT processor with pointer FIFOs based on FPGA G Zhong, H Zheng, ZH Jin, D Chen, Z Pang 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 122-125, 2011 | 15 | 2011 |
| Optimizing memory-access patterns for deep learning accelerators H Zheng, S Oh, H Wang, P Briggs, J Gai, A Jain, Y Liu, R Heaton, ... arXiv preprint arXiv:2002.12798, 2020 | 9 | 2020 |
| A gradual scheduling framework for problem size reduction and cross basic block parallelism exploitation in high-level synthesis H Zheng, Q Liu, J Li, D Chen, Z Wang 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 780-786, 2013 | 8 | 2013 |
| Efficient utilization of processing element array JT Huynh, R Diamant, H Zheng, Y Liu, A Jain, Y Wang, V Sharma, ... US Patent 11,741,350, 2023 | 6 | 2023 |
| New solutions for system-level and high-level synthesis W Zuo, H Zheng, ST Guruman, K Rupnow, D Chen 2014 International Symposium on Integrated Circuits (ISIC), 71-74, 2014 | 4 | 2014 |
| Loop-oriented neural network compilation H Zheng, PP Briggs, TJKE von Koch, T Kim, RR Huang US Patent 11,144,291, 2021 | 3 | 2021 |
| urger, A. Gr€ osslinger, and L. Pouchet,“Polly-polyhedral optimization in llvm,” T Grosser, H Zheng, R Aloor, A Simb Proc. 1st Int. Workshop Polyhedral Compilation Techn, 1-6, 2011 | 2 | 2011 |
| Compilation time reduction for memory and compute bound neural networks H Zheng, RR Huang, RJ Heaton US Patent 11,461,662, 2022 | 1 | 2022 |
| Dropout layer in a neural network processor J Gai, H Zheng, A Jain, RR Huang, V Vivekraja US Patent 12,159,218, 2024 | | 2024 |
| Compilation time reduction for memory and compute bound neural networks H Zheng, RR Huang, RJ Heaton US Patent 12,079,734, 2024 | | 2024 |
| Reconfigurable neural network processing based on subgraph recognition R Diamant, H Zheng, D Borkovic, H Li US Patent 12,045,611, 2024 | | 2024 |
| Compilation with caching of code analysis result H Zheng, P Ratnalikar US Patent 11,941,383, 2024 | | 2024 |
| Efficient utilization of processing element array JT Huynh, R Diamant, H Zheng, Y Liu, A Jain, Y Wang, V Sharma, ... US Patent App. 18/352,768, 2023 | | 2023 |
| Global modulo allocation in neural network compilation H Zheng, RR Huang, R Geva US Patent 11,809,849, 2023 | | 2023 |
| Reconfigurable neural network processing based on subgraph recognition R Diamant, H Zheng, D Borkovic, H Li US Patent 11,782,706, 2023 | | 2023 |
| State buffer memloc reshaping Y Yu, H Zheng, Q Liu US Patent 11,494,321, 2022 | | 2022 |
| Hierarchical partitioning of operators A Jain, Y Liu, H Zheng, JT Huynh, H Li, D Borkovic, J Zejda, RJ Heaton, ... US Patent App. 16/698,236, 2021 | | 2021 |
Swathi T. GurumaniEngineering ManagerVerified email at multicorewareinc.com
