| Polly-Polyhedral optimization in LLVM T Grosser, H Zheng, R Aloor, A Simbürger, A Größlinger, LN Pouchet Proceedings of the First International Workshop on Polyhedral Compilation …, 2011 | 199 | 2011 |
| Fast and effective placement and routing directed high-level synthesis for FPGAs H Zheng, ST Gurumani, K Rupnow, D Chen Proceedings of the 2014 ACM/SIGDA international symposium on Field …, 2014 | 32 | 2014 |
| High-level synthesis with behavioral-level multicycle path analysis H Zheng, ST Gurumani, L Yang, D Chen, K Rupnow IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 29 | 2014 |
| 1024-point pipeline FFT processor with pointer FIFOs based on FPGA G Zhong, H Zheng, ZH Jin, D Chen, Z Pang 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 122-125, 2011 | 13 | 2011 |
| A gradual scheduling framework for problem size reduction and cross basic block parallelism exploitation in high-level synthesis H Zheng, Q Liu, J Li, D Chen, Z Wang 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 780-786, 2013 | 7 | 2013 |
| New solutions for system-level and high-level synthesis W Zuo, H Zheng, ST Guruman, K Rupnow, D Chen 2014 International Symposium on Integrated Circuits (ISIC), 71-74, 2014 | 3 | 2014 |
Kyle RupnowASIC Architect, GoogleVerified email at google.com
