Floorplet: Performance-aware Floorplan Framework for Chiplet Integration S Chen, S Li, Z Zhuang, S Zheng, Z Liang, TY Ho, B Yu, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 | 10 | 2023 |
SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design S Chen, S Zheng, C Bai, W Zhao, S Yin, Y Bai, B Yu 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 207-212, 2024 | 7 | 2024 |
GTCO: Graph and Tensor Co-Design for Transformer-Based Image Recognition on Tensor Cores Y Bai, X Yao, Q Sun, W Zhao, S Chen, Z Wang, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 | 4 | 2023 |
WinoGen: A Highly Configurable Winograd Convolution IP Generator for Efficient CNN Acceleration on FPGA M Li, P Li, S Yin, S Chen, B Li, C Tong, J Yang, T Chen, B Yu Proceedings of the 61st ACM/IEEE Design Automation Conference, 1-6, 2024 | 1 | 2024 |
The Survey of 2.5 D Integrated Architecture: An EDA Perspective S Chen, H Zhang, Z Ling, J Zhai, B Yu | | 2025 |
The Survey of Chiplet-based Integrated Architecture: An EDA perspective S Chen, H Zhang, Z Ling, J Zhai, B Yu arXiv preprint arXiv:2411.04410, 2024 | | 2024 |