Analysis of the parasitic S/D resistance in multiple-gate FETs A Dixit, A Kottantharayil, N Collaert, M Goodwin, M Jurczak, K De Meyer IEEE Transactions on Electron Devices 52 (6), 1132-1140, 2005 | 447 | 2005 |
Bulk planar junctionless transistor (BPJLT): An attractive device alternative for scaling S Gundapaneni, S Ganguly, A Kottantharayil IEEE Electron device letters 32 (3), 261-263, 2011 | 283 | 2011 |
Effect of band-to-band tunneling on junctionless transistors S Gundapaneni, M Bajaj, RK Pandey, KVRM Murali, S Ganguly, ... IEEE Transactions on Electron Devices 59 (4), 1023-1029, 2012 | 255 | 2012 |
Multiple gate semiconductor device and method for forming same A Kottantharayil, R Loo US Patent App. 10/899,659, 2005 | 193 | 2005 |
Enhanced Electrostatic Integrity of Short-Channel Junctionless Transistor With High- Spacers S Gundapaneni, S Ganguly, A Kottantharayil IEEE Electron Device Letters 32 (10), 1325-1327, 2011 | 176 | 2011 |
Visual degradation in field-aged crystalline silicon PV modules in India and correlation with electrical degradation S Chattopadhyay, R Dubey, V Kuthanazhi, JJ John, CS Solanki, ... IEEE Journal of photovoltaics 4 (6), 1470-1476, 2014 | 117 | 2014 |
Study of soiling loss on photovoltaic modules with artificially deposited dust of different gravimetric densities and compositions collected from different locations in India JJ John, S Warade, G Tamizhmani, A Kottantharayil IEEE journal of photovoltaics 6 (1), 236-243, 2015 | 113 | 2015 |
Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography MJH Van Dal, N Collaert, G Doornbos, G Vellianitis, G Curatola, ... 2007 IEEE symposium on VLSI technology, 110-111, 2007 | 106 | 2007 |
Comprehensive study of performance degradation of field‐mounted photovoltaic modules in India R Dubey, S Chattopadhyay, V Kuthanazhi, A Kottantharayil, ... Energy Science & Engineering 5 (1), 51-64, 2017 | 97 | 2017 |
Dual-Spacer Device Architecture for the Improvement of Performance of Silicon n-Channel Tunnel FETs HG Virani, RBR Adari, A Kottantharayil IEEE transactions on electron devices 57 (10), 2410-2417, 2010 | 96 | 2010 |
A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node N Collaert, A Dixit, M Goodwin, KG Anil, R Rooyackers, B Degroote, ... IEEE Electron Device Letters 25 (8), 568-570, 2004 | 94 | 2004 |
Work function of Ni silicide phases on HfSiON and SiO/sub 2: NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/, and Ni/sub 3/Si fully silicided gates JA Kittl, MA Pawlak, A Lauwers, C Demeurisse, K Opsomer, KG Anil, ... IEEE electron device letters 27 (1), 34-36, 2005 | 88 | 2005 |
Layout density analysis of FinFETs KG Anil, K Henson, S Biesemans, N Collaert ESSDERC'03. 33rd Conference on European Solid-State Device Research, 2003 …, 2003 | 67 | 2003 |
Performance improvement of tall triple gate devices with strained SiN layers N Collaert, A De Keersgieter, KG Anil, R Rooyackers, G Eneman, ... IEEE electron device letters 26 (11), 820-822, 2005 | 66 | 2005 |
Mitigation of soiling by vertical mounting of bifacial modules S Bhaduri, A Kottantharayil IEEE Journal of Photovoltaics 9 (1), 240-244, 2018 | 65 | 2018 |
A CMOS compatible bulk FinFET-based ultra low energy leaky integrate and fire neuron for spiking neural networks D Chatterjee, A Kottantharayil IEEE Electron Device Letters 40 (8), 1301-1304, 2019 | 64 | 2019 |
GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices T Hoffmann, G Doornbos, I Ferain, N Collaert, P Zimmerman, M Goodwin, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 62 | 2005 |
Evaluation of soiling and potential mitigation approaches on photovoltaic glass A Einhorn, L Micheli, DC Miller, LJ Simpson, HR Moutinho, B To, ... IEEE Journal of Photovoltaics 9 (1), 233-239, 2018 | 56 | 2018 |
Silicon tunneling field-effect transistors with tunneling in line with the gate field IA Fischer, ASM Bakibillah, M Golve, D Hahnel, H Isemann, ... IEEE electron device letters 34 (2), 154-156, 2012 | 56 | 2012 |
Impact of stochastic mismatch on measured SRAM performance of FinFETs with resist/spacer-defined fins: Role of line-edge-roughness A Dixit, KG Anil, E Baravelli, P Roussel, A Mercha, C Gustin, M Bamal, ... 2006 International Electron Devices Meeting, 1-4, 2006 | 54 | 2006 |