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Jeffrey Goeders
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VTR 7.0: Next generation architecture and CAD system for FPGAs
J Luu, J Goeders, M Wainberg, A Somerville, T Yu, K Nasartschuk, M Nasr, ...
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2), 1-30, 2014
4602014
The VTR project: architecture and CAD for FPGAs from verilog to routing
J Rose, J Luu, CW Yu, O Densmore, J Goeders, A Somerville, KB Kent, ...
Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012
3652012
Effective FPGA debug for high-level synthesis generated circuits
J Goeders, SJE Wilton
2014 24th International Conference on Field Programmable Logic and …, 2014
732014
Signal-tracing techniques for in-system FPGA debugging of high-level synthesis circuits
J Goeders, SJE Wilton
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016
592016
Using dynamic signal-tracing to debug compiler-optimized HLS circuits on FPGAs
J Goeders, SJE Wilton
2015 IEEE 23rd annual international symposium on field-programmable custom …, 2015
562015
VersaPower: Power estimation for diverse FPGA architectures
JB Goeders, SJE Wilton
2012 International Conference on Field-Programmable Technology, 229-234, 2012
552012
Microcontroller compiler-assisted software fault tolerance
M Bohman, B James, MJ Wirthlin, H Quinn, J Goeders
IEEE Transactions on Nuclear Science 66 (1), 223-232, 2018
342018
Legup high-level synthesis
A Canis, J Choi, B Fort, B Syrowik, RL Lian, YT Chen, H Hsiao, J Goeders, ...
FPGAs for Software Programmers, 175-190, 2016
302016
Deterministic timing-driven parallel placement by simulated annealing using half-box window decomposition
JB Goeders, GGF Lemieux, SJE Wilton
2011 International Conference on Reconfigurable Computing and FPGAs, 41-48, 2011
242011
Applying compiler-automated software fault tolerance to multiple processor platforms
B James, H Quinn, M Wirthlin, J Goeders
IEEE Transactions on Nuclear Science 67 (1), 321-327, 2019
222019
Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques
PK Bussa, J Goeders, SJE Wilton
2017 27th International Conference on Field Programmable Logic and …, 2017
192017
Architecture exploration for HLS-oriented FPGA debug overlays
AS Jamal, J Goeders, SJE Wilton
Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018
182018
An FPGA overlay architecture supporting rapid implementation of functional changes during on-chip debug
AS Jamal, J Goeders, SJE Wilton
2018 28th International Conference on Field Programmable Logic and …, 2018
172018
Allowing software developers to debug HLS hardware
J Goeders, SJE Wilton
arXiv preprint arXiv:1508.06805, 2015
152015
Using round-robin tracepoints to debug multithreaded hls circuits on fpgas
J Goeders, SJE Wilton
2015 International Conference on Field Programmable Technology (FPT), 40-47, 2015
112015
Faster FPGA debug: Efficiently coupling trace instruments with user circuitry
E Hung, JB Goeders, SJE Wilton
Reconfigurable Computing: Architectures, Tools, and Applications: 10th …, 2014
112014
An overlay for rapid fpga debug of machine learning applications
DH Noronha, R Zhao, Z Que, J Goeders, W Luk, S Wilton
2019 International Conference on Field-Programmable Technology (ICFPT), 135-143, 2019
102019
Using novel configuration techniques for accelerated FPGA aging
T Gaskin, H Cook, W Stirk, R Lucas, J Goeders, B Hutchings
2020 30th International Conference on Field-Programmable Logic and …, 2020
82020
Demand driven assembly of fpga configurations using partial reconfiguration, ubuntu linux, and pynq
J Goeders, T Gaskin, B Hutchings
2018 IEEE 26th Annual International Symposium on Field-Programmable Custom …, 2018
82018
Fast Turnaround HLS Debugging using Dependency Analysis and Debug Overlays
AS Jamal, E Cahill, J Goeders, SJE Wilton
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 13 (1), 1-26, 2020
72020
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Articles 1–20