| High-throughput and energy-efficient VLSI architecture for ordered reliability bits GRAND SM Abbas, T Tonnellier, F Ercan, M Jalaleddine, WJ Gross IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022 | 42 | 2022 |
| High-throughput VLSI architecture for soft-decision decoding with ORBGRAND SM Abbas, T Tonnellier, F Ercan, M Jalaleddine, WJ Gross ICASSP 2021-2021 IEEE International Conference on Acoustics, Speech and …, 2021 | 25 | 2021 |
| List-GRAND: A practical way to achieve maximum likelihood decoding SM Abbas, M Jalaleddine, WJ Gross IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 (1), 43-54, 2022 | 22 | 2022 |
| High-throughput VLSI architecture for GRAND Markov order SM Abbas, M Jalaleddine, WJ Gross 2021 IEEE Workshop on Signal Processing Systems (SiPS), 158-163, 2021 | 17 | 2021 |
| GRAND for Rayleigh fading channels SM Abbas, M Jalaleddine, WJ Gross 2022 IEEE Globecom Workshops (GC Wkshps), 504-509, 2022 | 13 | 2022 |
| Hardware architecture for guessing random additive noise decoding Markov order (GRAND-MO) SM Abbas, M Jalaleddine, WJ Gross Journal of Signal Processing Systems 94 (10), 1047-1065, 2022 | 6 | 2022 |
| Towards achieving ultra reliable low latency communications using guessing random additive noise decoding M Jalaleddine McGill University (Canada), 2021 | 3 | 2021 |
| Guessing Random Additive Noise Decoding: A Hardware Perspective SM Abbas, M Jalaleddine, WJ Gross Springer Nature, 2023 | 2 | 2023 |
| Step-GRAND: A low latency universal soft-input decoder SM Abbas, CY Tsui, M Jalaleddine, WJ Gross 2023 IEEE Globecom Workshops (GC Wkshps), 1668-1673, 2023 | 1 | 2023 |
| Partial Ordered Statistics Decoding with Enhanced Error Patterns M Jalaleddine, H Zhou, J Li, WJ Gross 2023 IEEE International Symposium on Information Theory (ISIT), 1096-1100, 2023 | 1 | 2023 |
| Hardware architecture for fading-GRAND SM Abbas, M Jalaleddine, WJ Gross Guessing Random Additive Noise Decoding: A Hardware Perspective, 125-140, 2023 | 1 | 2023 |
| xSA: A Binary Cross-Entropy Simulated Annealing Polar Decoder R Seah, H Zhou, M Jalaleddine, WJ Gross 2023 12th International Symposium on Topics in Coding (ISTC), 1-5, 2023 | | 2023 |
| Hardware Architecture for Ordered Reliability Bits GRAND (ORBGRAND) SM Abbas, M Jalaleddine, F Ercan, T Tonnellier, W J. Gross Guessing Random Additive Noise Decoding: A Hardware Perspective, 39-71, 2023 | | 2023 |
| Guessing Random Additive Noise Decoding (GRAND) SM Abbas, M Jalaleddine, WJ Gross Guessing Random Additive Noise Decoding: A Hardware Perspective, 3-17, 2023 | | 2023 |
| A Survey of Recent GRAND Variants SM Abbas, M Jalaleddine, WJ Gross Guessing Random Additive Noise Decoding: A Hardware Perspective, 143-147, 2023 | | 2023 |
| Hardware Architecture for GRAND Markov Order (GRAND-MO) SM Abbas, M Jalaleddine, WJ Gross Guessing Random Additive Noise Decoding: A Hardware Perspective, 95-123, 2023 | | 2023 |
| Hardware Architecture for List GRAND (LGRAND) SM Abbas, M Jalaleddine, WJ Gross Guessing Random Additive Noise Decoding: A Hardware Perspective, 73-91, 2023 | | 2023 |
| Hardware Architecture for GRAND with ABandonment (GRANDAB) SM Abbas, M Jalaleddine, F Ercan, T Tonnellier, WJ Gross Guessing Random Additive Noise Decoding: A Hardware Perspective, 21-38, 2023 | | 2023 |
| Guessing Random Additive Noise Decoding SM Abbas, M Jalaleddine, WJ Gross | | |
Warren GrossProfessor of Electrical and Computer Engineering, McGill UniversityVerified email at mcgill.ca
