Fast extended test access via JTAG and FPGAs S Devadze, A Jutman, I Aleksejev, R Ubar 2009 International Test Conference, 1-7, 2009 | 27 | 2009 |
FPGA-based synthetic instrumentation for board test I Aleksejev, A Jutman, S Devadze, S Odintsov, T Wenzel 2012 IEEE International Test Conference, 1-10, 2012 | 23 | 2012 |
System and method for optimized board test and configuration S Devadze, A Jutman, I Aleksejev, K Shibin, T Wenzel US Patent 9,164,858, 2015 | 14 | 2015 |
Virtual reconfigurable scan-chains on FPGAs for optimized board test I Aleksejev, S Devadze, A Jutman, K Shibin 2015 16th Latin-American Test Symposium (LATS), 1-6, 2015 | 6 | 2015 |
Embedded synthetic instruments for Board-Level testing A Jutman, S Devadze, I Aleksejev, T Wenzel 2012 17th IEEE European Test Symposium (ETS), 1-1, 2012 | 6 | 2012 |
Turning JTAG inside out for fast extended test access S Devadze, A Jutman, I Aleksejev, R Ubar 2009 10th Latin American Test Workshop, 1-6, 2009 | 6 | 2009 |
Optimization of the store-and-generate based built-in self-test R Ubar, G Jervan, H Kruus, E Orasson, I Aleksejev 2006 International Biennial Baltic Electronics Conference, 1-4, 2006 | 5 | 2006 |
Reseeding using compaction of pre-generated LFSR sub-sequences A Jutman, I Aleksejev, J Raik, R Ubar 2008 15th IEEE International Conference on Electronics, Circuits and Systems …, 2008 | 4 | 2008 |
Teaching digital test with BIST analyzer A Jutman, A Tsertov, A Tsepurov, I Aleksejev, R Ubar, HD Wuttke 2008 19th EAEEIE Annual Conference, 123-128, 2008 | 4 | 2008 |
BIST analyzer: A training platform for SoC testing A Jutman, A Tsertov, A Tsepurov, I Aleksejev, R Ubar, HD Wuttke 2007 37th Annual Frontiers In Education Conference-Global Engineering …, 2007 | 4 | 2007 |
Embedded instrumentation toolbox for screening marginal defects and outliers for production S Odintsov, A Jutman, S Devadze, I Aleksejev 2017 IEEE AUTOTESTCON, 1-9, 2017 | 3 | 2017 |
Run-time reconfigurable instruments for advanced board-level testing I Aleksejev, A Jutman, S Devadze IEEE Instrumentation & Measurement Magazine 20 (4), 23-30, 2017 | 3 | 2017 |
On coverage of timing related faults at board level A Jutman, I Aleksejev, S Devadze 2016 21th IEEE European Test Symposium (ETS), 1-2, 2016 | 3 | 2016 |
FPGA-based Embedded Virtual Instrumentation I Aleksejev Tut Press, 2013 | 3 | 2013 |
Application of Sequential Test Set Compaction to LFSR Reseeding I Aleksejev, A Jutman, J Raik, R Ubar 2008 NORCHIP, 102-107, 2008 | 3 | 2008 |
Ways for board and system test to benefit from FPGA embedded instrumentation H Ehrenberg, S Odintsov, S Devadze, A Jutman, I Aleksejev, T Wenzel 2019 IEEE AUTOTESTCON, 1-10, 2019 | 2 | 2019 |
Sequential Test Set Compaction in LFSR Reseeding A Jutman, I Aleksejev, J Raik Design and Test Technology for Dependable Systems-on-Chip, 476-493, 2011 | 2 | 2011 |
E-Learning Environment for WEB-Based Study of Testing R Ubar, A Jutman, J Raik, S Devadze, M Jenihhin, I Aleksejev, ... Proc. of the 8th European Workshop on Microelectronics Education-EWME 2010 …, 2010 | 2 | 2010 |
Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures I Aleksejev, S Devadze, A Jutman, K Shibin Journal of Electronic Testing 32, 245-255, 2016 | 1 | 2016 |
Complex delay fault reasoning with sequential 7-valued algebra J Kousaar, R Ubar, I Aleksejev 2015 16th Latin-American Test Symposium (LATS), 1-6, 2015 | | 2015 |