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Mahdi Taheri
Mahdi Taheri
PhD researcher at TalTech
Verified email at taltech.ee - Homepage
Title
Cited by
Cited by
Year
Deepaxe: A framework for exploration of approximation and reliability trade-offs in dnn accelerators
M Taheri, M Riazati, MH Ahmadilivani, M Jenihhin, M Daneshtalab, J Raik, ...
2023 24th International Symposium on Quality Electronic Design (ISQED), 1-8, 2023
82023
A high-performance MEMRISTOR-based Smith-Waterman DNA sequence alignment Using FPNI structure
M Taheri, H Zandevakili, A Mahani
Journal of Applied Research in Electrical Engineering 1 (1), 2021
52021
Development and hardware acceleration of a novel 2-DBWA-MEM DNA sequencing alignment algorithm
M Taheri, A Mahani
52021
DeepVigor: Vulnerability Value Ranges and Factors for DNNs' Reliability Assessment
MH Ahmadilivani, M Taheri, J Raik, M Daneshtalab, M Jenihhin
arXiv preprint arXiv:2303.06931, 2023
32023
Dnn hardware reliability assessment and enhancement
M Taheri
32022
Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme
S Sheikhpur, M Taheri, MS Ansari, A Mahani
IET Computers & Digital Techniques 15 (3), 1-14, 2021
32021
DMR-based Technique for Fault Tolerant AES S-box Architecture
M Taheri, S Sheikhpour, MS Ansari, A Mahani
1 st Conference on Applied Research in Electrical Engineering (AREE), 2021
32021
Appraiser: Dnn fault resilience analysis employing approximation errors
M Taheri, MH Ahmadilivani, M Jenihhin, M Daneshtalab, J Raik
2023 26th International Symposium on Design and Diagnostics of Electronic …, 2023
22023
Noise-Tolerance GPU-based Age Estimation Using ResNet-50
M Taheri, M Taheri, A Hadjahmadi
arXiv preprint arXiv:2305.00848, 2023
22023
A Novel Fault-Tolerant Logic Style with Self-Checking Capability
M Taheri, S Sheikhpour, A Mahani, M Jenihhin
2022 IEEE 28th International Symposium on On-Line Testing and Robust System …, 2022
22022
A fault-resistant architecture for aes s-box architecture
M Taheri, S Sheikhpour, MS Ansari, A Mahani
Journal of Applied Research in Electrical Engineering 1 (1), 86-92, 2022
22022
A Novel 2-D BWA-MEM FPGA Accelerator for Short-Read Mapping of the Whole Human Genome
M Taheri, A Mahani
Journal of Applied Research in Electrical Engineering 1 (2), 203-210, 2021
22021
A systematic literature review on hardware reliability assessment methods for deep neural networks
MH Ahmadilivani, M Taheri, J Raik, M Daneshtalab, M Jenihhin
ACM Computing Surveys 56 (6), 1-39, 2024
12024
Special Session: Approximation and Fault Resiliency of DNN Accelerators
MH Ahmadilivani, M Barbareschi, S Barone, A Bosio, M Daneshtalab, ...
2023 IEEE 41st VLSI Test Symposium (VTS), 1-10, 2023
12023
Hardware acceleration of the novel two dimensional Burrows‐Wheeler Aligner algorithm with maximal exact matches seed extension kernel
M Taheri, MS Ansari, S Magierowski, A Mahani
IET Circuits, Devices & Systems 15 (2), 94-103, 2021
12021
Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators
M Taheri, N Cherezova, MS Ansari, M Jenihhin, A Mahani, ...
arXiv preprint arXiv:2401.09509, 2024
2024
Enhancing Fault Resilience of QNNs by Selective Neuron Splitting
MH Ahmadilivani, M Taheri, J Raik, M Daneshtalab, M Jenihhin
arXiv preprint arXiv:2306.09973, 2023
2023
LRDB: LSTM Raw data DNA Base-caller based on long-short term models in an active learning environment
A Rezaei, M Taheri, A Mahani, S Magierowski
arXiv preprint arXiv:2303.08915, 2023
2023
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