| Ultra low-voltage/low-power digital floating-gate circuits Y Berg, DT Wisland, TS Lande IEEE Transactions on circuits and systems II: Analog and digital signal …, 1999 | 127 | 1999 |
| Programming floating-gate circuits with UV-activated conductances Y Berg, TS Lande, O Naess IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2001 | 96 | 2001 |
| State-of-the-art power management circuits for piezoelectric energy harvesters F Dell'Anna, T Dong, P Li, Y Wen, Z Yang, MR Casu, M Azadmehr, Y Berg IEEE Circuits and Systems Magazine 18 (3), 27-48, 2018 | 83 | 2018 |
| Novel recharge semi-floating-gate CMOS logic for multiple-valued systems Y Berg, S Aunet, O Minnotahari, M Hovin 2003 IEEE International Symposium on Circuits and Systems (ISCAS) 5, V-V, 2003 | 78 | 2003 |
| Ultra-low-voltage floating-gate transconductance amplifiers Y Berg, TS Lande, O Naess, H Gundersen IEEE Transactions on circuits and systems II: Analog and digital signal …, 2001 | 75 | 2001 |
| Programmable floating-gate MOS logic for low-power operation Y Berg, ST Lande 1997 IEEE International Symposium on Circuits and Systems (ISCAS) 3, 1792-1795, 1997 | 50 | 1997 |
| An analog feed-forward neural network with on-chip learning Y Berg, RL Sigvartsen, TS Lande, A Abusland Analog Integrated Circuits and Signal Processing 9, 65-75, 1996 | 40 | 1996 |
| Ultra low voltage CMOS gates Y Berg, O Mirmotahari, PA Norseng, S Aunet 2006 13th IEEE International Conference on Electronics, Circuits and Systems …, 2006 | 37 | 2006 |
| FLOGIC-Floating-gate logic for low-power operation TS Lande, DT Wisland, T Soether, Y Berg Proceedings of Third International Conference on Electronics, Circuits, and …, 1996 | 35 | 1996 |
| High speed ultra low voltage CMOS inverter Y Berg, O Mirmotahari, JG Lomsdalen, S Aunet 2008 IEEE Computer Society Annual Symposium on VLSI, 122-127, 2008 | 33 | 2008 |
| Area efficient circuit tuning with floating-gate techniques Y Berg, TS Lande 1999 IEEE International Symposium on Circuits and Systems (ISCAS) 2, 396-399, 1999 | 33 | 1999 |
| Reconfigurable subthreshold CMOS perceptron S Aunet, B Oelmann, S Abdalla, Y Berg 2004 IEEE International Joint Conference on Neural Networks (IEEE Cat. No …, 2004 | 32 | 2004 |
| A novel balanced ternary adder using recharged semi-floating gate devices H Gundersen, Y Berg 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 18-18, 2006 | 27 | 2006 |
| Pseudo floating-gate inverter with feedback control Y Berg, O Mirmotahari, S Aunet 2006 IFIP International Conference on Very Large Scale Integration, 272-277, 2006 | 26 | 2006 |
| Real-time reconfigurable linear threshold elements implemented in floating-gate CMOS S Aunet, Y Berg, T Sæther IEEE Transactions on Neural Networks 14 (5), 1244-1256, 2003 | 26 | 2003 |
| Low-voltage floating-gate current mirrors Y Berg, TS Lande, S Naess Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit …, 1997 | 23 | 1997 |
| Three sub-fJ power-delay-product subthreshold CMOS gates S Aunet, Y Berg IFIP VLSI SoC 1719, 2005 | 22 | 2005 |
| A novel D-latch in multiple-valued semi-floating-gate recharged logic O Mirmotahari, Y Berg Proceedings. 34th International Symposium on Multiple-Valued Logic, 210-213, 2004 | 22 | 2004 |
| Four-MOSFET floating-gate UV-programmable elements for multifunction binary logic S Aunet, Y Berg, O Tjore, Ø Næss, T Sæther Proceedings of the 5th World Multiconference on Systemics, Cybernetics and …, 2001 | 22 | 2001 |
| New SRAM design using body bias technique for ultra low power applications F Moradi, DT Wisland, H Mahmoodi, Y Berg, TV Cao 2010 11th International Symposium on Quality Electronic Design (ISQED), 468-471, 2010 | 21 | 2010 |
