| A theory of timed automata R Alur, DL Dill Theoretical computer science 126 (2), 183-235, 1994 | 9580 | 1994 |
| Symbolic model checking: 1020 states and beyond JR Burch, EM Clarke, KL McMillan, DL Dill, LJ Hwang Information and computation 98 (2), 142-170, 1992 | 4394 | 1992 |
| Automata for modeling real-time systems R Alur, D Dill International colloquium on automata, languages, and programming, 322-335, 1990 | 1586 | 1990 |
| EXE: Automatically generating inputs of death C Cadar, V Ganesh, PM Pawlowski, DL Dill, DR Engler ACM Transactions on Information and System Security (TISSEC) 12 (2), 1-38, 2008 | 1492 | 2008 |
| Model-checking for real-time systems R Alur, C Courcoubetis, D Dill [1990] Proceedings. Fifth Annual IEEE Symposium on Logic in Computer Science …, 1990 | 1387 | 1990 |
| Reluplex: An efficient SMT solver for verifying deep neural networks G Katz, C Barrett, DL Dill, K Julian, MJ Kochenderfer International conference on computer aided verification, 97-117, 2017 | 1364 | 2017 |
| Model-checking in dense real-time R Alur, C Courcoubetis, D Dill Information and computation 104 (1), 2-34, 1993 | 1335 | 1993 |
| Timing assumptions and verification of finite-state concurrent systems DL Dill International Conference on Computer Aided Verification, 197-212, 1989 | 1074 | 1989 |
| Symbolic model checking for sequential circuit verification JR Burch, EM Clarke, DE Long, KL McMillan, DL Dill IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1994 | 850 | 1994 |
| A decision procedure for bit-vectors and arrays V Ganesh, DL Dill International conference on computer aided verification, 519-531, 2007 | 793 | 2007 |
| Trace theory for automatic hierarchical verification of speed-independent circuits DL Dill MIT press, 1989 | 793 | 1989 |
| Automatic verification of pipelined microprocessor control JR Burch, DL Dill International Conference on Computer Aided Verification, 68-80, 1994 | 791 | 1994 |
| Better verification through symmetry C Norris Ip, DL Dill Formal methods in system design 9 (1), 41-75, 1996 | 779* | 1996 |
| Sequential circuit verification using symbolic model checking JR Burch, EM Clarke, KL McMillan, DL Dill 27th ACM/IEEE Design Automation Conference, 46-51, 1990 | 709 | 1990 |
| Protocol verification as a hardware design aid. DL Dill, AJ Drexler, AJ Hu, CH Yang ICCD 92, 522-525, 1992 | 639 | 1992 |
| {CMC}: A Pragmatic Approach to Model Checking Real Code M Musuvathi, DYW Park, A Chou, DR Engler, DL Dill 5th Symposium on Operating Systems Design and Implementation (OSDI 02), 2002 | 535 | 2002 |
| The Mur ϕ verification system DL Dill International Conference on Computer Aided Verification, 390-393, 1996 | 494 | 1996 |
| Automated identification of stratifying signatures in cellular subpopulations RV Bruggner, B Bodenmiller, DL Dill, RJ Tibshirani, GP Nolan Proceedings of the National Academy of Sciences 111 (26), E2770-E2777, 2014 | 388 | 2014 |
| Parallelizing the Murϕ verifier U Stern, DL Dill International Conference on Computer Aided Verification, 256-267, 1997 | 377* | 1997 |
| Experience with predicate abstraction S Das, DL Dill, S Park International Conference on Computer Aided Verification, 160-171, 1999 | 346 | 1999 |
