| PUMA: A programmable ultra-efficient memristor-based accelerator for machine learning inference A Ankit, IE Hajj, SR Chalamalasetti, G Ndu, M Foltin, RS Williams, ... Proceedings of the twenty-fourth international conference on architectural …, 2019 | 455 | 2019 |
| An FPGA memcached appliance SR Chalamalasetti, K Lim, M Wright, A AuYoung, P Ranganathan, ... Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2013 | 130 | 2013 |
| Panther: A programmable architecture for neural network training harnessing energy-efficient reram A Ankit, I El Hajj, SR Chalamalasetti, S Agarwal, M Marinella, M Foltin, ... IEEE Transactions on Computers 69 (8), 1128-1142, 2020 | 96 | 2020 |
| MORA-an architecture and programming model for a resource efficient coarse grained reconfigurable processor SR Chalamalasetti, S Purohit, M Margala, W Vanderbauwhede 2009 NASA/ESA Conference on Adaptive Hardware and Systems, 389-396, 2009 | 47 | 2009 |
| Mixed precision quantization for ReRAM-based DNN inference accelerators S Huang, A Ankit, P Silveira, R Antunes, SR Chalamalasetti, I El Hajj, ... Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021 | 44 | 2021 |
| Analysis and modeling of collaborative execution strategies for heterogeneous CPU-FPGA architectures S Huang, LW Chang, I El Hajj, S Garcia de Gonzalo, J Gómez-Luna, ... Proceedings of the 2019 ACM/SPEC International Conference on Performance …, 2019 | 44 | 2019 |
| Memristor TCAMs accelerate regular expression matching for network intrusion detection CE Graves, C Li, X Sheng, W Ma, SR Chalamalasetti, D Miller, ... IEEE Transactions on Nanotechnology 18, 963-970, 2019 | 43 | 2019 |
| Hardware-software co-design for an analog-digital accelerator for machine learning J Ambrosi, A Ankit, R Antunes, SR Chalamalasetti, S Chatterjee, I El Hajj, ... 2018 IEEE International Conference on Rebooting Computing (ICRC), 1-13, 2018 | 39 | 2018 |
| High level programming framework for FPGAs in the data center O Segal, M Margala, SR Chalamalasetti, M Wright 2014 24th International Conference on Field Programmable Logic and …, 2014 | 26 | 2014 |
| Evaluating FPGA-acceleration for real-time unstructured search SR Chalamalasetti, M Margala, W Vanderbauwhede, M Wright, ... 2012 IEEE International Symposium on Performance Analysis of Systems …, 2012 | 21 | 2012 |
| A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model SR Chalamalasetti, W Vanderbauwhede, S Purohit, M Margala 2009 International Conference on Field Programmable Logic and Applications …, 2009 | 20 | 2009 |
| Generalize or die: Operating systems support for memristor-based accelerators P Bruel, SR Chalamalasetti, C Dalton, I El Hajj, A Goldman, C Graves, ... 2017 IEEE International Conference on Rebooting Computing (ICRC), 1-8, 2017 | 18 | 2017 |
| High level programming for heterogeneous architectures O Segal, M Margala, SR Chalamalasetti, M Wright arXiv preprint arXiv:1408.4964, 2014 | 17 | 2014 |
| Design and evaluation of high-performance processing elements for reconfigurable systems SS Purohit, SR Chalamalasetti, M Margala, WA Vanderbauwhede IEEE transactions on very large scale integration (VLSI) systems 21 (10 …, 2012 | 16 | 2012 |
| Embedded Systems: Hardware, Design and Implementation K Iniewski John Wiley & Sons, 2012 | 14 | 2012 |
| Power-efficient high throughput reconfigurable datapath design for portable multimedia devices S Purohit, SR Chalamalasetti, M Margala, P Corsonello 2008 International Conference on Reconfigurable Computing and FPGAs, 217-222, 2008 | 14 | 2008 |
| Autotuning high-level synthesis for FPGAs using OpenTuner and LegUp P Bruel, A Goldman, SR Chalamalasetti, D Milojicic 2017 International Conference on ReConFigurable Computing and FPGAs …, 2017 | 13 | 2017 |
| A C++-embedded Domain-Specific Language for programming the MORA soft processor array W Vanderbauwhede, M Margala, SR Chalamalasetti, S Purohit ASAP 2010-21st IEEE International Conference on Application-specific Systems …, 2010 | 13 | 2010 |
| Throughput/resource-efficient reconfigurable processor for multimedia applications S Purohit, SR Chalamalasetti, M Margala, W Vanderbauwhede IEEE transactions on very large scale integration (VLSI) systems 21 (7 …, 2012 | 12 | 2012 |
| Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor. W Vanderbauwhede, M Margala, SR Chalamalasetti, S Purohit ERSA, 195-201, 2009 | 12 | 2009 |
Martin MargalaProfessor and Director, School of Computing and Informatics, University of Louisiana at LafayetteVerified email at louisiana.edu
