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Wladyslaw Grabinski
Wladyslaw Grabinski
GMC Suisse, MOS-AK, EPFL, ETHZ, ITE (IMiF)
Verified email at grabinski.ch - Homepage
Title
Cited by
Cited by
Year
TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model
A Biswas, SS Dan, C Le Royer, W Grabinski, AM Ionescu
Microelectronic Engineering 98, 334-337, 2012
1332012
RF distortion analysis with compact MOSFET models
P Bendix, P Rakers, P Wagh, L Lemaitre, W Grabinski, CC McAndrew, ...
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat …, 2004
802004
An adjusted constant-current method to determine saturated and linear mode threshold voltage of MOSFETs
A Bazigos, M Bucher, J Assenmacher, S Decker, W Grabinski, ...
IEEE Transactions on Electron Devices 58 (11), 3751-3758, 2011
752011
Transistor level modeling for analog/RF IC design
W Grabinski, B Nauwelaers, D Schreurs
Springer Science & Business Media, 2006
542006
Investigation of tunnel field-effect transistors as a capacitor-less memory cell
A Biswas, N Dagtekin, W Grabinski, A Bazigos, C Le Royer, JM Hartmann, ...
Applied Physics Letters 104 (9), 2014
492014
Electrical modeling of a pressure sensor MOSFET
JM Sallese, W Grabinski, V Meyer, C Bassin, P Fazan
Sensors and Actuators A: Physical 94 (1-2), 53-58, 2001
492001
Accounting for quantum effects and polysilicon depletion from weak to strong inversion in a charge-based design-oriented MOSFET model
C Lallement, JM Sallese, M Bucher, W Grabinski, PC Fazan
IEEE Transactions on Electron Devices 50 (2), 406-417, 2003
352003
EKV3. 0: An advanced charge based MOS transistor model. A design-oriented MOS transistor compact model
M Bucher, A Bazigos, F Krummenacher, JM Sallese, C Enz
Transistor Level Modeling for Analog/RF IC Design, 67-95, 2006
292006
Accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-section and high uniaxial tensile strain
M Najmzadeh, D Bouvet, W Grabinski, JM Sallese, AM Ionescu
Solid-state electronics 74, 114-120, 2012
252012
Steep slope VO2switches for wide-band (DC-40 GHz) reconfigurable electronics
WA Vitale, A Paone, M Fernández-Bolaños, A Bazigos, W Grabinski, ...
72nd Device Research Conference, 29-30, 2014
222014
Power/HVMOS Devices Compact Modeling
W Grabinski, T Gneiting
Springer Verlag, 2010
222010
Compact device modeling using Verilog-AMS and ADMS
L Lemaitre, W Grabiński, C McAndrew
Electron Technology: Internet Journal 35 (3), 1-5, 2003
202003
Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm
M Najmzadeh, M Berthomé, JM Sallese, W Grabinski, AM Ionescu
Solid-state electronics 98, 55-62, 2014
172014
Extended charges modeling for deep submicron CMOS
M Bucher, JM Sallese, C Lallement, W Grabinski, CC Enz, ...
Proc. of the Int. Semiconductor Device Research Symp., 397-400, 1999
161999
A novel extraction method and compact model for the steepness estimation of FDSOI TFET lateral junction
SS Dan, A Biswas, C Le Royer, W Grabinski, AM Ionescu
IEEE electron device letters 33 (2), 140-142, 2011
142011
Compact modelling of ultra deep submicron CMOS devices
W GRABIŃSKI, JM SALLESE, M BUCHER, F KRUMMENACHER
Bulletin of the Polish Academy of Sciences. Technical Sciences 50, 2002
142002
Advancements in DC and RF Mosfet modeling with the EPFL-EKV charge based model
JM Sallese, W Grabinski, AS Porret, M Bucher, C Lallement, ...
8th Int. Conf. MIXDES, 45-52, 2001
122001
Process control monitor based extraction procedure for statistical compact MOSFET modeling
M Yakupov, D Tomaszewski, W Grabinski
Proceedings of the 17th International Conference Mixed Design of Integrated …, 2010
112010
Large-signal network analyzer measurements and their use in device modeling
E Vandamme, W Grabinski, D Schreurs, T Gneiting
MIXDES 2002, 2002
102002
„The EKV model parameter extraction based on its IC-CAP USERC implementation”
W Grabinski, M Bucher, F Krummenacher
Eur. IC-CAP Users Meet, 1999
91999
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