Payman Zarkesh-Ha
Title
Cited by
Cited by
Year
Interconnect opportunities for gigascale integration
JD Meindl, JA Davis, P Zarkesh-Ha, CS Patel, KP Martin, PA Kohl
IBM journal of research and development 46 (2.3), 245-263, 2002
2142002
Impact of three-dimensional architectures on interconnects in gigascale integration
JW Joyner, R Venkatesan, P Zarkesh-Ha, JA Davis, JD Meindl
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (6), 922-928, 2001
1042001
A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC)
JW Joyner, P Zarkesh-Ha, JD Meindl
Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No …, 2001
912001
Characterization and modeling of clock skew with process variations
P Zarkesh-Ha, T Mule, JD Meindl
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No …, 1999
871999
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
P Zarkesh-Ha, JA Davis, JD Meindl
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (6), 649-659, 2000
802000
A three-dimensional stochastic wire-length distribution for variable separation of strata
JW Joyner, P Zarkesh-Ha, JA Davis, JD Meindl
Proceedings of the IEEE 2000 International Interconnect Technology …, 2000
632000
Global interconnect design in a three-dimensional system-on-a-chip
JW Joyner, P Zarkesh-Ha, JD Meindl
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (4), 367-372, 2004
612004
Interconnecting device opportunities for gigascale integration (GSI)
JD Meindl, R Venkatesan, JA Davis, J Joyner, A Naeemi, P Zarkesh-Ha, ...
International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001
572001
Double gate ion sensitive field effect transistor
P Zarkesh-Ha, SRJ Brueck, J Edwards
US Patent App. 14/347,713, 2014
502014
Prediction of interconnect fan-out distribution using Rent's rule
P Zarkesh-Ha, JA Davis, W Loh, JD Meindl
Proceedings of the 2000 international workshop on System-level interconnect …, 2000
462000
A compact physical via blockage model
Q Chen, JA Davis, P Zarkesh-Ha, JD Meindl
IEEE transactions on very large scale integration (VLSI) systems 8 (6), 689-692, 2000
432000
Energy recycling in clock distribution networks using on-chip inductors
P Zarkesh-Ha, W Loh
US Patent 7,082,580, 2006
372006
Impact of interconnect pattern density information on a 90 nm technology ASIC design flow
P Zarkesh-Ha, S Lakshminarayanan, K Doniger, W Loh, P Wright
Fourth International Symposium on Quality Electronic Design, 2003 …, 2003
332003
On a pin versus gate relationship for heterogeneous systems: Heterogeneous Rent's rule
P Zarkesh-Ha, JA Davis, W Loh, JD Meindl
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No …, 1998
301998
Modeling NoC traffic locality and energy consumption with rent's communication probability distribution
GBP Bezerra, S Forrest, M Moses, A Davis, P Zarkesh-Ha
Proceedings of the 12th ACM/IEEE international workshop on System level …, 2010
292010
Stochastic net length distributions for global interconnects in a heterogeneous system-on-a-chip
P Zarkesh-Ha, JD Meindl
1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No …, 1998
271998
A global interconnect design window for a three-dimensional system-on-a-chip
JW Joyner, P Zarkesh-Ha, JD Meindl
Proceedings of the IEEE 2001 International Interconnect Technology …, 2001
262001
Sea of leads: A disruptive paradigm for a system-on-a-chip (SoC)
A Naeemi, GS Patel, MS Bakir, P Zarkesh-Ha, KP Martin, JD Meindl
2001 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2001
262001
An integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC)
P Zarkesh-Ha, JD Meindl
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No …, 2000
262000
Stochastic analysis and design guidelines for CNFETs in gigascale integrated systems
P Zarkesh-Ha, AAM Shahi
IEEE Transactions on Electron Devices 58 (2), 530-539, 2010
252010
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