Ravi Rajwar

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James GoodmanProfessor Emeritus of Computer Science, University of Wisconsin-MadisonVerified email at cs.wisc.edu
Haitham AkkaryMIFrontiers CorporationVerified email at mifrontiers.com
James R LarusProfessor Emeritus, EPFLVerified email at larusstone.org
Craig ZillesProfessor of Computer Science, University of Illinois at Urbana-ChampaignVerified email at illinois.edu
Tim HarrisMicrosoftVerified email at microsoft.com
Martin DixonGoogleVerified email at google.com
Maurice HerlihyAn Wang Professor of Computer Science, Brown UniversityVerified email at cs.brown.edu
Mikko LipastiProfessor, Electrical and Computer Engineering, University of Wisconsin-MadisonVerified email at engr.wisc.edu
Harold W. "Trey" CainQualcomm ResearchVerified email at qti.qualcomm.com
Sai BalakrishnanPlatform Architect, GoogleVerified email at google.com
Richard M. YooSoftware Engineer, Google Inc.Verified email at google.com
Tomas KarnagelObserve IncVerified email at observeinc.com
Wolfgang LehnerTechnische Universität DresdenVerified email at tu-dresden.de
Roman DementievIntelVerified email at intel.com
Benjamin SchlegelGoogleVerified email at google.com
Thomas LeglerVerified email at sap.com
Milo M. K. MartinGoogle (Former Associate Professor, University of Pennsylvania)Verified email at google.com
Amin VahdatGoogleVerified email at cs.ucsd.edu
J. Eliot B. MossProfessor Emeritus of Information and Computer Sciences, University of Massachusetts AmherstVerified email at cs.umass.edu
Luis RodriguesINESC-ID, Instituto Superior Técnico, Universidade de LisboaVerified email at tecnico.ulisboa.pt

Ravi Rajwar

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Computing Platforms Computer Architecture Software


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Gemini 1.5: Unlocking multimodal understanding across millions of tokens of context G Team, P Georgiev, VI Lei, R Burnell, L Bai, A Gulati, G Tanzer, ... arXiv preprint arXiv:2403.05530, 2024	720	2024
Transactional memory T Harris, JR Larus, R Rajwar Morgan & Claypool, 2010	696	2010
Speculative lock elision: Enabling highly concurrent multithreaded execution R Rajwar, JR Goodman Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture …, 2001	669	2001
Transactional memory JR Larus, R Rajwar Springer Nature, 2022	605	2022
Virtualizing transactional memory R Rajwar, M Herlihy, K Lai 32nd International Symposium on Computer Architecture (ISCA'05), 494-505, 2005	597	2005
Transactional lock-free execution of lock-based programs R Rajwar, JR Goodman ACM SIGOPS Operating Systems Review 36 (5), 5-17, 2002	454	2002
Checkpoint processing and recovery: Towards scalable large instruction window processors H Akkary, R Rajwar, ST Srinivasan Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003	395	2003
Performance Evaluation of Intel(R) Transactional Synchronization Extensions for High-Performance Computing R Yoo, C Hughes, K Lai, R Rajwar Supercomputing 2013, 2013	375	2013
The impact of performance asymmetry in emerging multicore architectures S Balakrishnan, R Rajwar, M Upton, K Lai 32nd International Symposium on Computer Architecture (ISCA'05), 506-517, 2005	375	2005
Haswell: The Fourth-Generation Intel Core Processor P Hammarlund, AJ Martinez, AA Bajwa, DL Hill, E Hallnor, H Jiang, ... IEEE MICRO 34 (2), 2014	368	2014
Continual flow pipelines ST Srinivasan, R Rajwar, H Akkary, A Gandhi, M Upton ACM SIGARCH Computer Architecture News 32 (5), 107-119, 2004	260	2004
Haswell: A family of IA 22 nm processors N Kurd, M Chowdhury, E Burton, TP Thomas, C Mozak, B Boswell, ... IEEE Journal of Solid-State Circuits 50 (1), 49-58, 2014	232	2014
An architectural evaluation of Java TPC-W HW Cain, R Rajwar, M Marden, MH Lipasti Proceedings HPCA Seventh International Symposium on High-Performance …, 2001	189	2001
Hardware atomicity for reliable software speculation N Neelakantam, R Rajwar, S Srinivas, U Srinivasan, C Zilles Proceedings of the 34th Annual International Symposium on Computer …, 2007	93	2007
Improving In-Memory Database Index Performance with Intel(R) Transactional Synchronization Extensions T Karnagel, R Dementiev, R Rajwar, K Lai, T Legler, B Schlegel, ... 20th International Symposium on High-Performance Computer Architecture, 2014	88	2014
Scalable load and store processing in latency tolerant processors A Gandhi, H Akkary, R Rajwar, ST Srinivasasn, K Lai 32nd International Symposium on Computer Architecture (ISCA'05), 446-457, 2005	86	2005
Improving the throughput of synchronization by insertion of delays R Rajwar, A Kagi, JR Goodman Proceedings Sixth International Symposium on High-Performance Computer …, 2000	52	2000
Transactional memory (synthesis lectures on computer architecture) T Harris, J Larus, R Rajwar Synthesis Lectures on Computer Architecture. Morgan and Claypool, 2010	51	2010
Characterizing a Java implementation of TPC-W T Bezenek, T Cain, R Dickson, T Heil, M Martin, C McCurdy, R Rajwar, ... Proceedings of the Third Workshop On Computer Architecture Evaluation Using …, 2000	51	2000
Transactional execution: Toward reliable, high-performance multithreading R Rajwar, J Goodman IEEE Micro 23 (6), 117-125, 2003	48	2003

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