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Cesar Albenes Zeferino
Cesar Albenes Zeferino
Professor of Computer Science, University of Vale do Itajaí
Verified email at univali.br
Title
Cited by
Cited by
Year
SoCIN: a parametric and scalable network-on-chip
CA Zeferino, AA Susin
16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003 …, 2003
3652003
SPIN: a scalable, packet switched, on-chip micro-network
A Adriahantenaina, H Charlery, A Greiner, L Mortiez, CA Zeferino
2003 Design, Automation and Test in Europe Conference and Exhibition, 70-73 …, 2003
3332003
RASoC: A router soft-core for networks-on-chip
CA Zeferino, ME Kreutz, AA Susin
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004
1582004
A study on communication issues for systems-on-chip
CA Zeferino, ME Kreutz, L Carro, AA Susin
Proceedings. 15th Symposium on Integrated Circuits and Systems Design, 121-126, 2002
1382002
The impact of NoC reuse on the testing of core-based systems
É Cota, M Kreutz, CA Zeferino, L Carro, M Lubaszewski, A Susin
Proceedings. 21st VLSI Test Symposium, 2003., 128-133, 2003
1222003
A review of techniques for implementing elliptic curve point multiplication on hardware
A Verri Lucca, GA Mariano Sborz, VRQ Leithardt, M Beko, ...
Journal of Sensor and Actuator Networks 10 (1), 3, 2020
622020
A solution for dynamic management of user profiles in IoT environments
V Leithardt, D Santos, L Silva, F Viel, C Zeferino, J Silva
IEEE Latin America Transactions 18 (07), 1193-1199, 2020
592020
Paris: a parameterizable interconnect switch for networks-on-chip
CA Zeferino, FGME Santo, AA Susin
Proceedings of the 17th symposium on Integrated circuits and system design …, 2004
572004
Redes-em-Chip: arquiteturas e modelos para avaliação de área e desempenho
CA Zeferino
562003
A low-cost fault-tolerant RISC-V processor for space systems
DA Santos, LM Luza, CA Zeferino, L Dilillo, DR Melo
2020 15th Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 1-5, 2020
502020
Communication architectures for system-on-chip
ME Kreutz, L Carro, CA Zeferino, AA Susin
Symposium on Integrated Circuits and Systems Design, 14-19, 2001
322001
Security mechanisms to improve the availability of a Network-on-Chip
S Baron, MS Wangham, CA Zeferino
2013 IEEE 20th International Conference on Electronics, Circuits, and …, 2013
302013
A survey of the RISC-V architecture software support
BW Mezger, DA Santos, L Dilillo, CA Zeferino, DR Melo
IEEE Access 10, 51394-51411, 2022
292022
An Efficient Interface for the Integration of IoT Devices with Smart Grids
F Viel, L Augusto Silva, VRQ Leithardt, JF De Paz Santana, ...
Sensors 20 (10), 2849, 2020
282020
Hyperspectral image classification: An analysis employing CNN, LSTM, transformer, and attention mechanism
F Viel, RC Maciel, LO Seman, CA Zeferino, EA Bezerra, VRQ Leithardt
IEEE access 11, 24835-24850, 2023
262023
Internet of Things: Concepts, architectures and technologies
F Viel, LA Silva, RQV Leithardt, CA Zeferino
2018 13th IEEE International Conference on Industry Applications (INDUSCON …, 2018
252018
Hybrid impedance-admittance control for upper limb exoskeleton using electromyography
LDL da Silva, TF Pereira, VRQ Leithardt, LO Seman, CA Zeferino
Applied Sciences 10 (20), 7146, 2020
242020
Bipide–ambiente de desenvolvimento integrado para a arquitetura dos processadores BIP
PV Vieira, ALA Raabe, CA Zeferino
Revista Brasileira de Informática na Educação 18 (01), 32, 2010
232010
Performance and security evaluation on a blockchain architecture for license plate recognition systems
I Sestrem Ochôa, V Reis Quietinho Leithardt, L Calbusch, ...
Applied Sciences 11 (3), 1255, 2021
222021
Reliability analysis of a fault-tolerant RISC-V system-on-chip
DA Santos, LM Luza, L Dilillo, CA Zeferino, DR Melo
Microelectronics Reliability 125, 114346, 2021
212021
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