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Manupa Karunaratne
Manupa Karunaratne
Verified email at comp.nus.edu.sg
Title
Cited by
Cited by
Year
Hycube: A cgra with reconfigurable single-cycle multi-hop interconnect
M Karunaratne, AK Mohite, T Mitra, LS Peh
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
1112017
4K real-time HEVC decoder on an FPGA
M Abeydeera, M Karunaratne, G Karunaratne, K De Silva, A Pasqual
IEEE Transactions on Circuits and Systems for Video Technology 26 (1), 236-249, 2015
582015
Locus: Low-power customizable many-core architecture for wearables
C Tan, A Kulkarni, V Venkataramani, M Karunaratne, T Mitra, LS Peh
ACM Transactions on Embedded Computing Systems (TECS) 17 (1), 1-26, 2017
332017
Stitch: Fusible heterogeneous accelerators enmeshed with many-core architecture for wearables
C Tan, M Karunaratne, T Mitra, LS Peh
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018
322018
Dnestmap: mapping deeply-nested loops on ultra-low power cgras
M Karunaratne, C Tan, A Kulkarni, T Mitra, LS Peh
Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018
212018
Cascade: High throughput data streaming via decoupled access-execute cgra
D Wijerathne, Z Li, M Karunarathne, A Pathania, T Mitra
ACM Transactions on Embedded Computing Systems (TECS) 18 (5s), 1-26, 2019
172019
4d-cgra: Introducing branch dimension to spatio-temporal application mapping on cgras
M Karunaratne, D Wijerathne, T Mitra, LS Peh
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
162019
Hycube: A 0.9 v 26.4 mops/mw, 290 pj/op, power efficient accelerator for iot applications
B Wang, M Karunarathne, A Kulkarni, T Mitra, LS Peh
2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 133-136, 2019
132019
Stitch: Fusible heterogeneous accelerators enmeshed with many-core architecture for wearables. In 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA)
C Tan, M Karunaratne, T Mitra, LS Peh
IEEE, 2018
92018
Hycube: A cgra with reconfigurable single-cycle multi-hop interconnect. In 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)
M Karunaratne, AK Mohite, T Mitra, LS Peh
IEEE, 2017
42017
Morpher: An Open-Source Integrated Compilation and Simulation Framework for CGRA
D Wijerathne, Z Li, M Karunaratne, LS Peh, T Mitra
Fifth Workshop on Open-Source EDA Technology (WOSET), 2022
12022
HyCUBE: A 0.9 V 26.4 MOPS/mW, 290 pJ/cycle, power efficient accelerator for IoT applications
B Wang, M Karunarathne, A Kulkarni, T Mitra, LS Peh
A-SSCC, 0
1
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